1. Field of the Invention
This invention relates to MOSFET semiconductor devices and more particularly to capacitive structures therein.
2. Description of Related Art
The "neuron" MOSFET (neuMOS or nu(Greek symbol) MOS) (so named because it is considered to be analogous in function to a biological neuron) with double polysilicon utilized as coupling capacitor has the problem of polysilicon stringers which are unwanted fragments of polysilicon which can cause shorting between lines. One way of removing stringers is by overetching, but this causes a problem of a narrowing of the oxide layer which can cause short circuiting through the interpolysilicon oxide layer between the polysilicon 1 layer and the polysilicon 2 layer.
FIGS. 6A-6C show a prior art device.
FIG. 6A is a plan view with input gate lines C1, C2, C3 and C4, a V.sub.SS line, a V.sub.DD line, and a floating gate FG.
FIG. 6B is a section taken along line X-X' in FIG. 6A through floating gate FG. The substrate includes a P-silicon substrate with an N region separated by FOX regions and with a floating gate overlying the N region, the FOX regions and the P-sub. The input gate lines C.sub.1, C.sub.2, C.sub.3 and C.sub.4 are located above the floating gate FG, separated by dielectric D. In the dielectric D in FIGS. 6A and 6B are stringers S, about the periphery of V.sub.SS line, a V.sub.DD line, and a floating gate FG.
The circuit of the device of FIGS. 6A and 6B is shown in FIG. 6C with conductors C.sub.1, C.sub.2, C.sub.3 . . . C.sub.n connected to voltage sources V.sub.1, V.sub.2, V.sub.3 . . . V.sub.n, floating gate FG and the transistors below connected to V.sub.SS and V.sub.DD.
See Shibata et al "Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations", IEEE Transactions on Electron Devices, Vol. 39, No. 6, p 1444-1455 (June, 1992) which has the stringer problems described above, although they are not described there.
U.S. Pat. No. 5,215,934 of Tzeng shows a different thickness depending upon where the ion implantation has been applied or is absent from the silicon surface with argon, boron, antimony, arsenic, or any group III or IV dopant applied for enhancing the rate of oxidation in silicon which has been damaged by the process of implantation of such dopants. The variable thickness is employed for providing a two tiered tunnel oxide upon which a floating gate and control gate are formed across the two tiers for the purpose of as stated at Col. 7, lines 11-12 "reducing drain disturbance in EEPROM arrays . . . " It also states at Col. 2, lines 52-54 "it is also desired to thicken the gate oxide near the drain region to reduce drain disturbance phenomena . . . "
U.S. Pat. No. 5,038,184 Chiang et al shows a thin film varactor structure.
U.S. Pat. No. 5,119,267 of Sano et al, U.S. Pat. No. 5,018,000 of Yamada et al, U.S. Pat. No. 4,890,191 of Rokos; U.S. Pat. No. 4,841,320 of Aso; U.S. Pat. No. 4,805,071 of Hutter et al; and U.S. Pat. No. 4,211,941 of Schade show processes for making capacitors. However, these processes fail to form a CMOS neuron device.